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low skew, 1-to-24 differential- to-lvcmos/lvttl fanout buffer ics8344-01 idt ? / ics ? lvcmos/lvttl fanout buffer 1 ics8344ay-01 rev. c september 9, 2008 g eneral d escription the ics8344-01 is a low voltage, low skew fanout buffer and a member of the hiperclocks? family of high performance clock solutions from idt. the ics8344-01 has two selectable clock in- puts. the clkx, nclkx pairs can accept most standard differential input levels. the ics8344-01 is designed to translate any differential signal level to lvcmos/lvttl lev- els. the low impedance lvcmos/lvttl outputs are designed to drive 50 series or parallel terminated transmission lines. the effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. redundant clock applications can make use of the dual clock inputs which also facilitate board level testing. the clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. the outputs are driven low when disabled. the ics8344-01 is characterized at full 3.3v, full 2.5v and mixed 3.3v input and 2.5v output operating supply modes. guaranteed output and part-to-part skew characteristics make the ics8344-01 ideal for those clock distribution applications demanding well defined performance and repeatability. f eatures ? twenty-four lvcmos/lvttl outputs, 7 typical output impedance ? two selectable differential clkx, nclkx inputs ? clk0, nclk0 and clk1, nclk1 pairs can accept the following input levels: lvds, lvpecl, lvhstl, sstl, hcsl ? output frequency up to 250mhz ? translates any single ended input signal to lvcmos/lvttl with resistor bias on nclk input ? synchronous clock enable ? additive phase jitter rms: 0.21ps (typical) ? output skew: 200ps (maximum) ? part-to-part skew: 900ps (maximum) ? bank skew: 85ps (maximum) ? propagation delay: 5ns (maximum) ? output supply modes: core/output 3.3v/3.3v 2.5v/2.5v 3.3v/2.5v ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages b lock d iagram p in a ssignment hiperclocks? ic s q0:q7 q8:q15 q16:q23 clk_sel clk0 nclk0 clk1 nclk1 clk_en oe le q nd 0 1 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 q16 q17 v ddo gnd q18 q19 q20 q21 v ddo gnd q22 q23 q7 q6 v ddo gnd q5 q4 q3 q2 v ddo gnd q1 q0 nc oe clk_en clk0 nclk0 v dd gnd clk1 nclk1 v dd gnd clk_sel q8 q9 v ddo gnd q10 q11 q12 q13 v ddo gnd q14 q15 48-lead lqfp 7mm x 7mm x 1.4mm package body y package top view ics8344-01 pulldown pulldown pullup pulldown pullup pullup pullup
idt ? / ics ? lvcmos/lvttl fanout buffer 2 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 6 , 5 , 2 , 1 2 1 , 1 1 , 8 , 7 9 1 q , 8 1 q , 7 1 q , 6 1 q 3 2 q , 2 2 q , 1 2 q , 0 2 q t u p t u o7 . s t u p t u o 3 2 q u r h t 6 1 q . e c n a d e p m i t u p t u o l a c i p y t , 8 2 , 9 , 3 5 4 , 9 3 , 4 3 v o d d r e w o p. v 5 . 2 r o v 3 . 3 t c e n n o c . s n i p y l p p u s t u p t u o , 8 1 , 4 1 , 0 1 , 4 6 4 , 0 4 , 3 3 , 7 2 d n gr e w o p. d n u o r g o t t c e n n o c . d n u o r g y l p p u s r e w o p 3 1l e s _ k l ct u p n in w o d l l u p , s t u p n i k l c n , 1 k l c s t c e l e s , h g i h n e h w . t u p n i t c e l e s k c o l c . s t u p n i 0 k l c n , 0 k l c s t c e l e s , w o l n e h w . s s l e v e l e c a f r e t n i l t t v l / s o m c v l 9 1 , 5 1v d d r e w o p. v 5 . 2 r o v 3 . 3 t c e n n o c . s n i p y l p p u s e v i t i s o p 6 11 k l c nt u p n ip u l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i 7 11 k l ct u p n in w o d l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i - n o n 0 20 k l c nt u p n ip u l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i 1 20 k l ct u p n in w o d l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i - n o n 2 2n e _ k l ct u p n ip u l l u p . s t u p t u o k c o l c g n i l b a s i d d n a g n i l b a n e r o f l o r t n o c g n i z i n o r h c n y s . s l e v e l e c a f r e t n i s o m c v l 3 2e ot u p n ip u l l u p s t u p t u o f o g n i l b a s i d d n a g n i l b a n e s l o r t n o c . e l b a n e t u p t u o . 3 2 q u r h t 0 q 4 2c nd e s u n u. t c e n n o c o n 0 3 , 9 2 , 6 2 , 5 2 6 3 , 5 3 , 2 3 , 1 3 3 q , 2 q , 1 q , 0 q 7 q , 6 q , 5 q , 4 q t u p t u o7 . s t u p t u o 7 q u r h t 0 q . e c n a d e p m i t u p t u o l a c i p y t 2 4 , 1 4 , 8 3 , 7 3 8 4 , 7 4 , 4 4 , 3 4 1 1 q , 0 1 q , 9 q , 8 q 5 1 q , 4 1 q , 3 1 q , 2 1 q t u p t u o7 . s t u p t u o 5 1 q u r h t 8 q . e c n a d e p m i t u p t u o l a c i p y t : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i , 0 k l c n , 0 k l c 1 k l c n , 1 k l c 4f p , l e s _ k l c e o , n e _ k l c 4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v o d d v 5 6 4 . 3 =3 2f p v o d d v 5 7 6 . 2 =6 1f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r t u o e c n a d e p m i t u p t u o 7
idt ? / ics ? lvcmos/lvttl fanout buffer 3 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer t able 3a. o utput e nable f unction t able t able 3b. c lock s elect f unction t able t able 3c. c lock i nput f unction t able t u p n i l o r t n o ck c o l c l e s _ k l c0 k l c n , 0 k l c1 k l c n , 1 k l c ) t l u a f e d ( 0d e t c e l e sd e t c e l e s - e d 1d e t c e l e s - e dd e t c e l e s s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p e o1 k l c , 0 k l c1 k l c n , 0 k l c n3 2 q u r h t 0 q ) t l u a f e d ( 1) t l u a f e d ( 0) t l u a f e d ( 1w o ld e d n e e l g n i s o t l a i t n e r e f f i dg n i t r e v n i n o n 11 0 h g i hd e d n e e l g n i s o t l a i t n e r e f f i dg n i t r e v n i n o n 10 1 e t o n ; d e s a i bw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 1 e t o n ; d e s a i bh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 e t o n ; d e s a i b0h g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i 11 e t o n ; d e s a i b1w o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i s e s s u c s i d h c i h w , 1 e r u g i f , 8 e g a p n o n o i t c e s n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n l a i t n e r e f f i d e h t g n i r i w . s l e v e l d e d n e - e l g n i s t p e c c a o t t u p n i 3 , 2 , 1 s k n a b s t u p n is t u p t u o e on e _ k l c3 2 q - 0 q 0x z - i h 10 1 e t o n . e t a t s w o l c i g o l n i d e l b a s i d ) t l u a f e d ( 1) t l u a f e d ( 11 e t o n . d e l b a n e g n i l l a f e h t o t s u o n o r h c n y s s i n o i t c n u f e l b a s i d d n a e l b a n e k c o l c e h t : 1 e t o n . k c o l c e c n e r e f e r d e t c e l e s e h t f o e g d e
idt ? / ics ? lvcmos/lvttl fanout buffer 4 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer t able 4a. p ower s upply dc c haracteristics , v dd = v ddo = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p t n e c s e i u q 5 9a m t able 4d. lvcmos/lvttl dc c haracteristics , v dd = v ddo = 3.3v5%, t a = 0c to 70c t able 4b. p ower s upply dc c haracteristics , v dd = 3.3v5%, v ddo = 2.5v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p t n e c s e i u q 5 9a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i , n e _ k l c , l e s _ k l c e o 28 . 3v v l i e g a t l o v w o l t u p n i , n e _ k l c , l e s _ k l c e o 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i e o , n e _ k l cv d d v = n i v 5 6 4 . 3 =5a l e s _ k l cv d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i e o , n e _ k l cv d d v , 5 6 4 . 3 = n i v 0 =0 5 1 -a l e s _ k l cv d d v , 5 6 4 . 3 = n i v 0 =5 -a v h o e g a t l o v h g i h t u p t u o v d d v = o d d v 5 3 1 . 3 = i h o a m 6 3 - = 7 . 2v v l o e g a t l o v w o l t u p t u o v d d v = o d d v 5 3 1 . 3 = i l o a m 6 3 = 5 . 0v a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4c. p ower s upply dc c haracteristics , v dd = v ddo = 2.5v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 25 . 25 2 6 . 2v v o d d e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p t n e c s e i u q 5 9a m
idt ? / ics ? lvcmos/lvttl fanout buffer 5 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer t able 4e. lvcmos/lvttl dc c haracteristics , v dd = 3.3v5%, v ddo = 2.5v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i , n e _ k l c , l e s _ k l c e o 28 . 3v v l i e g a t l o v w o l t u p n i , n e _ k l c , l e s _ k l c e o 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i e o , n e _ k l cv d d v = n i v 5 6 4 . 3 =5a l e s _ k l cv d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i e o , n e _ k l cv d d v , 5 6 4 . 3 = n i v 0 =0 5 1 -a l e s _ k l cv d d v , 5 6 4 . 3 = n i v 0 =5 -a v h o e g a t l o v h g i h t u p t u o v d d v 5 3 1 . 3 = v o d d v 5 7 3 . 2 = i h o a m 7 2 - = 9 . 1v v l o e g a t l o v w o l t u p t u o v d d v 5 3 1 . 3 = v o d d v 5 7 3 . 2 = i l o a m 7 2 = 4 . 0v t able 4f. lvcmos/lvttl dc c haracteristics , v dd = v ddo = 2.5v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i , n e _ k l c , l e s _ k l c e o 29 . 2v v l i e g a t l o v w o l t u p n i , n e _ k l c , l e s _ k l c e o 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i e o , n e _ k l cv d d v = n i v 5 2 6 . 2 =5a l e s _ k l cv d d v = n i v 5 2 6 . 2 =0 5 1a i l i t n e r r u c w o l t u p n i e o , n e _ k l cv d d v , 5 2 6 . 2 = n i v 0 =0 5 1 -a l e s _ k l cv d d v , 5 2 6 . 2 = n i v 0 =5 -a v h o e g a t l o v h g i h t u p t u o v d d v = o d d v 5 7 3 . 2 = i h o a m 7 2 - = 9 . 1v v l o e g a t l o v w o l t u p t u o v d d v = o d d v 5 7 3 . 2 = i l o a m 7 2 = 4 . 0v
idt ? / ics ? lvcmos/lvttl fanout buffer 6 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer t able 4i. d ifferential dc c haracteristics , v dd = v ddo = 2.5v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 1 k l c n , 0 k l c nv d d v = n i v 5 2 6 . 2 =5a 1 k l c , 0 k l cv d d v = n i v 5 2 6 . 2 =0 5 1a i l i t n e r r u c w o l t u p n i 1 k l c n , 0 k l c nv d d v , v 5 2 6 . 2 = n i v 0 =0 5 1 -a 1 k l c , 0 k l cv d d v , v 5 2 6 . 2 = n i v 0 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 3 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 9 . 02v s i 1 k l c n , 1 k l c d n a 0 k l c n , 0 k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n v d d . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . t able 4h. d ifferential dc c haracteristics , v dd = 3.3v5%, v ddo = 2.5v5%, t a = 0c to 70c t able 4g. d ifferential dc c haracteristics , v dd = v ddo = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 1 k l c n , 0 k l c nv d d v = n i v 5 6 4 . 3 =5a 1 k l c , 0 k l cv d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i 1 k l c n , 0 k l c n v d d , v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a 1 k l c , 0 k l c v d d , v 5 6 4 . 3 = v n i v 0 = 5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 3 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 9 . 02v v s i 1 k l c n , 1 k l c d n a 0 k l c n , 0 k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n + d d . v 3 . 0 v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 1 k l c n , 0 k l c nv d d v = n i v 5 6 4 . 3 =5a 1 k l c , 0 k l cv d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i 1 k l c n , 0 k l c nv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a 1 k l c , 0 k l cv d d v , v 5 6 4 . 3 = n i v 0 =5 -a v p p e g a t l o v t u p n i k a e p o t - k a e p 3 . 03 . 1v v r m c 2 , 1 e t o n : e g a t l o v t u p n i e d o m n o m m o c 9 . 02v v s i 1 k l c n , 1 k l c d n a 0 k l c n , 0 k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n d d . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i .
idt ? / ics ? lvcmos/lvttl fanout buffer 7 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer t able 5. ac c haracteristics , v dd = v ddo = 3.3v5%; v dd = 3.3v 5%, v ddo = 2.5v 5%; v dd = v ddo = 2.5v 5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o m u m i x a m 0 5 2z h m t d p 1 e t o n , y a l e d n o i t a g a p o r pf z h m 0 0 25 . 25s n t t i j , r e t t i j e s a h p e v i t i d d a r e f f u b e s a h p e v i t i d d a o t r e f e r ; s m r n o i t c e s r e t t i j : e g n a r n o i t a r g e t n i , z h m 2 5 . 5 5 1 z h m 0 2 - z h k 2 1 1 2 . 0s p t ) b ( k s ; w e k s k n a b 6 , 2 e t o n ] 7 : 0 [ q e g d e g n i s i r e h t n o d e r u s a e m v f o o d d 2 / 5 8s p ] 5 1 : 8 [ q 0 8 1s p ] 3 2 : 6 1 [ q 0 0 1s p t ) o ( k s6 , 3 e t o n ; w e k s t u p t u o e g d e g n i s i r e h t n o d e r u s a e m v f o o d d 2 / 0 0 2s p t ) p p ( k s6 , 4 e t o n ; w e k s t r a p - o t - t r a p e g d e g n i s i r e h t n o d e r u s a e m v f o o d d 2 / 0 0 9s p t r 5 e t o n ; e m i t e s i r t u p t u o% 0 7 o t % 0 30 0 20 0 8s p t f 5 e t o n ; e m i t l l a f t u p t u o% 0 7 o t % 0 30 0 20 0 8s p c d oe l c y c y t u d t u p t u o f z h m 0 0 2t e l c y c 5 2 . 0 - 2 /t e l c y c 2 /t e l c y c 5 2 . 0 + 2 /% z h m 0 0 2 = f5 2 . 25 . 25 7 . 2s n t n e 5 e t o n ; e m i t e l b a n e t u p t u oz h m 0 1 = f5s n t s i d 5 e t o n ; e m i t e l b a s i d t u p t u oz h m 0 1 = f4s n v d n a z h m 0 0 2 t a d e r u s a e m s r e t e m a r a p l l a p p . e s i w r e h t o d e t o n s s e l n u p y t v o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n o d d . 2 / . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v e m a s e h t t a s t u p t u o f o k n a b a n i h t i w w e k s s a d e n i f e d : 2 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o f o s k n a b s s o r c a w e k s s a d e n i f e d : 3 e t o n v t a d e r u s a e m . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b s a d e n i f e d : 4 e t o n o d d . 2 / . n o i t c u d o r p n i d e t s e t t o n . n o i t a z i r e t c a r a h c y b d e e t n a r a u g e r a s r e t e m a r a p e s e h t : 5 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 6 e t o n
idt ? / ics ? lvcmos/lvttl fanout buffer 8 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer a dditive p hase j itter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z additive phase jitter @ 155.52mhz (12khz to 20mhz) = 0.21ps typical
idt ? / ics ? lvcmos/lvttl fanout buffer 9 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer p arameter m easurement i nformation 3.3v c ore /2.5v o utput l oad ac t est c ircuit 3.3v o utput l oad ac t est c ircuit scope qx lvcmos gnd 1.65v5% -1.65v5% scope qx lvcmos gnd 1.25v5% -1.25v5% d ifferential i nput l evel v cmr cross points v pp gnd clk0, clk1 nclk0, nclk1 v dd p art - to -p art s kew t sk(o) v ddo 2 v ddo 2 qx qy o utput s kew t sk(pp) v ddo 2 v ddo 2 qx qy part 1 part 2 v dd , v ddo v dd , v ddo 2.5v o utput l oad ac t est c ircuit scope qx lvcmos gnd v ddo v dd 2.05v5% -1.25v5% 1.25v5%
idt ? / ics ? lvcmos/lvttl fanout buffer 10 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer p ropagation d elay o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f nclk0, nclk1 clk0, clk1 q0:q23 t pd o utput d uty c ycle /p ulse w idth /p eriod t period t pw t period odc = v ddo 2 x 100% t pw q0:q23
idt ? / ics ? lvcmos/lvttl fanout buffer 11 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer a pplication i nformation f igure 1. s ingle e nded s ignal d riving d ifferential i nput figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clkx nclkx vdd i nputs : clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utput : all unused lvcmos output can be left floating. there should be no trace attached.
idt ? / ics ? lvcmos/lvttl fanout buffer 12 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer f igure 2c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2 e show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are f igure 2a. h i p er c lock s clk/nclk i nput d riven by idt h i p er c lock s lvhstl d river examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 2a, the input termination applies for idt hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 2e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
idt ? / ics ? lvcmos/lvttl fanout buffer 13 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer r eliability i nformation t ransistor c ount the transistor count for ics8344-01 is: 1503 t able 6. ja vs . a ir f low t able for 48 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
idt ? / ics ? lvcmos/lvttl fanout buffer 14 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s c b b m u m i n i ml a n i m o nm u m i x a m n 8 4 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 7 1 . 02 2 . 07 2 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 5 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 5 . 5 e c i s a b 0 5 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -8 0 . 0 p ackage o utline - y s uffix for 48 l ead lqfp t able 7. p ackage d imensions reference document: jedec publication 95, ms-026
idt ? / ics ? lvcmos/lvttl fanout buffer 15 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments. t able 8. o rdering i nformation part/order number marking package shipping packaging temperature 8344ay-01 ics8344ay-01 48 lead lqfp tray 0c to 70c 8344ay-01t ics8344ay-01 48 lead lqfp 1000 tape & reel 0c to 70c 8344AY-01LF ics8344ay0ll 48 lead "lead-free" lqfp tray 0c to 70c 8344AY-01LFt ics8344ay0ll 48 lead "lead-free" lqfp 1000 tape & reel 0c to 70c note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant.
idt ? / ics ? lvcmos/lvttl fanout buffer 16 ics8344ay-01 rev. c september 9, 2008 ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b a 4 d 4 g 4 4 5 6 i d e s i v e r d d . x a m a m 5 9 o t . x a m a m 0 6 m o r f w o r i d e s i v e r d d . x a m a m 5 9 o t . x a m a m 0 6 m o r f w o r i d e s i v e r d d . x a m a m 5 9 o t . x a m a m 0 6 m o r f w o r 1 0 / 6 / 8 ba 5 7 0 1 - 8 . 4 e t o n d n a 1 e t o n d e s i v e r . s e r u g i f t n e m e r u s a e m r e t e m a r a p d e t a d p u . s e t o n n o i t a r e d i s n o c r e w o p d e t e l e d 1 0 / 3 1 / 2 1 b1 . m a r g a i d k c o l b d e t a d p u 1 0 / 8 1 / 2 1 b8 4 1 . e l b a t n o i t a m r o f n i g n i r e d r o e h t n i d e t c e r r o c s a w o p y t a 1 0 0 2 , 8 1 l i r p a n o 4 4 3 8 s c i s a w n o i t c e r r o c e h ta4 4 3 8 s c i m o r f 1 0 - yb. 1 0 - y 2 0 / 4 2 / 7 b 1 0 1 1 1 4 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f d e d d a . s n i p t u p t u o d n a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r d e d d a . e c a f r e t n i t u p n i k c o l c l a i t n e r e f f i d . e t o n d n a g n i k r a m , r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o . t a m r o f t e e h s a t a d d e t a d p u 6 0 / 6 2 / 0 1 ba 33 . e l b a t d e t a d p u - e l b a t n o i t c n u f e l b a n e t u p t u o 7 0 / 0 1 / 5 c c 3 t - a 3 t 5 8 1 1 2 3 7 8 5 1 d e d d a p u l l u p d n a n w o d l l u p . m a r g a i d k c o l b o t . t e l l u b r e t t i j e s a h p e v i t i d d a d e d d a - n o i t c e s s e r u t a e f c d d a - e l b a t s c i t s i r e t c a r a h c n i p d p . s c e p s d e d d a - s e l b a t n o i t c n u f t l u a f e d . s n o i t i d n o c o t . w o r r e t t i j e s a h p e v i t i d d a d e d d a - e l b a t s c i t s i r e t c a r a h c c a . t o l p r e t t i j e s a h p e v i t i d d a d e d d a r e b m u n r e d r o / t r a p m o r f x i f e r p s c i d e v o m e r - e l b a t n o i t a m r o f n i g n i r e d r o . n m u l o c 8 0 / 8 / 9 c 2 t2c n i n i . l e s _ k l c h t i w l e s - k l c d e c a l p e r , w o r 8 0 / 9 / 9
ics8344-01 low skew, 1-to-24 differential-to-lvcmos/lvttl fanout buffer innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt for tech support netcom@idt.com +480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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